This invention relates to a control circuit for an EEPROM (Electrically Erasable Programmable Read Only Memory), more particularly to a control circuit generating a high voltage pulse enabling a rewrite function of EEPROM data with low voltage and low power consumption.
There are various kinds of EEPROMs available not only for use as a single unit but for constituting an one-chip microcomputer in combination with a microprocessor, which can be constructed as a CMOS structure.
A semiconductor integrated circuit in which the EEPROM is incorporated has a wide variety of applications such as replacement of a mechanical switch, an IC card having function which stores and adjusts operational procedures of a calculator or stores and refreshes data. (Ex. See NIKKEI ELECTRONICS, Oct. 21, 1985 P. 127)
Since the conventional EEPROM, however, employs a 5V power supply and needs a data rewrite cycle, it is difficult to be incorporated into the semiconductor integrated circuit utilized in watches, electric calculators, cameras, toys or IC cards driven by a solar cell.
FIG. 6 shows a block diagram of a control circuit for EEPROM with 5V single power supply operation generating a high voltage pulse for data write/erase/read.
The power supply voltage of 5V is applied to a clock pulse generation circuit 1 so that a clock pulse train having a frequency of 5-10MH.sub.z and a peak wave value of 5V can be achieved.
When the clock pulse is applied to a voltage booster circuit 2, a step-up voltage of 23-25V can be output.
FIG. 7 shows an example of the conventional voltage booster circuit having 10-13 booster stages which are adequate for obtaining a step-up voltage of 20-25V from a source voltage of 5V.
The high voltage of 20-25V generated by the booster circuit 2 is applied to a regulator circuit 3 which stabilizes the high voltage to a constant level voltage.
FIG. 8(A) shows a concrete circuit of the regulator circuit, the output voltage of which is 18-20V in direct current (D.C.).
A wave shaping circuit 4 generates a high voltage pulse which is necessary to write/erase data of cells of the EEPROM.
The high voltage pulse requires a peak wave value of 18-20V and a constant rising rate, for example, 16V/ms.
When the rising rate is too sharp, the reliability of the cells of the EEPROM will be deteriorated.
One embodiment of the concrete wave shaping circuit is shown in FIG. 8(B).
There is provided a high voltage switch circuit 5 to switch the high voltage pulse generated by the wave shaping circuit 4 to a writing direction or to an erasing direction, interchangeably.
FIG. 8(C) shows a concrete circuit of the high voltage switch circuit 5.
The high voltage pulse is switched interchangeably by the high voltage switch circuit 5 such a manner that the high voltage pulse is applied to a drain electrode of the memory cell in accordance with a writing signal W in case of writing, whereas it is applied to a gate electrode of the memory cell in accordance with an erasing signal E on erasing.
A memory cell 6 is constituted by being arrayed a plurality of FETs with a double layer silicon gate structure comprising a source electrode , a drain electrode, a floating gate and a gate electrode.
One embodiment of the concrete circuit is shown in FIG. 9.
The writing function to the memory cell 6 is performed such that the high voltage pulse is applied between the drain and the gate with the gate electrode being fixed to zero volt.
The erasing cycle is performed such that the high voltage pulse is applied between the gate and the drain with the drain electrode being fixed to zero volt.